Nonvolatile semiconductor memories, particularly flash memories, include a CAM protection circuit associated with each sector of the memory. The CAM protection circuit stores an indication of whether the associated sector is protected from programming/erasing. An associated logic circuit reads the information stored in the CAM protection circuit each time a user requests erasing or programming of the sector. The logic circuit enables or disables the program/erase operation depending on the information stored in the CAM protection circuit.
A prior art CAM protection circuit 10 is shown in FIG. 1. Each sector of a flash memory (not shown) is associated with such a CAM protection circuit 10. The CAM protection circuit includes first and second flash memory cells 12, 14, a latch 16, and a pass transistor 18 connecting the latch 16 to the memory cells 12,14. When the sector associated with the CAM protection circuit 10 is programmed, the flash memory cells 12,14 are programmed with a bit indicating whether the sector is protected from erasing and programming.
The first memory cell 12 includes drain and source terminals connected respectively to gate, drain, and source terminals of the second memory cell 14. The gate terminals of the memory cells 12,14 are coupled to a control signal WL and the source terminals are connected to a voltage reference Source, which is ground when the memory cells are read by the latch 16. The drain terminals of the memory cells 12,14 coupled to a source terminal of the pass transistor 18, which has a gate terminal connected to a voltage reference VB and a drain terminal connected to the latch 16. The reference voltage VB, which is relatively insensitive to variations in the supply voltage Vdd, biases the drain terminals of the memory cells 12,14 to a voltage VB minus Vth (threshold voltage of the pass transistor 18).
The latch 16 includes a first inverter 20 having in input coupled to an input terminal 22 of the latch and an output coupled to an output terminal 24 of the latch. The latch 16 also includes a second inverter 26 having in input coupled to the output terminal 24 and an output coupled to the input terminal 22. The output terminal 24 also is coupled to a logic circuit (not shown) that reads the status information stored in the CAM protection circuit 10 and determines from that status information whether to allow programming or erasing of the corresponding sector of the memory. Also coupled to the input terminal 22 of the latch 16 is the drain terminal of a reset transistor 28 having a source terminal coupled to ground and a gate terminal coupled to a reset signal.
The first and second inverters 20,26 are substantially identical, and therefore for simplicity, only the first inverter 20 will be described in detail. The first inverter 20 includes a pull-down transistor 30 having a source terminal coupled to ground, a drain terminal coupled to the output terminal 24 of the latch and a gate terminal coupled to the input terminal 22 of the latch. The first inverter 20 also includes a pull-up transistor 32 having a drain terminal coupled to a source voltage Vdd, a source terminal coupled to the output terminal 24 of the latch 16 and a gate terminal coupled to the input terminal 22 of the latch.
When the device that includes the nonvolatile memory and the CAM protection circuit 10 is turned on, the reset signal goes high which turns on the reset transistor 28 thereby causing the latch 16 to initially assume a high logic state at the output terminal 24. When the user desires to program or erase the corresponding memory sector, the gates of the first and second memory cells 12,14 are biased by the signal WL and the sources are brought to ground. If the memory cells 12,14 are erased, current is drawn from the pull-up transistor 32 through the pass transistor 18 and the memory cells to ground. This switches the latch 16 (the output terminal 24 goes to a low logic state), which means that the corresponding sector is unprotected. If the memory cells 12,14 are programmed, there is no current drawn and the latch 16 does not change logic status, which means that the corresponding sector remains protected.
In this type of circuit 10, is important that the pull-up transistor 32 be sufficiently resistive to guarantee a relatively easy switching. However, to have a trip point (inversion voltage of the latch 16) sufficiently central between the supply voltage Vdd and ground, the other components of the latch should be dimensioned appropriately.
One problem with the CAM protection circuit 10 is that if the supply voltage Vdd is sufficiently high, the current through the memory cells 12,14 may not be sufficient to switch the logic state of the latch 16. FIG. 2 shows the current through the pull-up transistor 32 necessary for switching the latch 16 for various values of the supply voltage Vdd. FIG. 2 shows that for supply voltages Vdd ranging from 2.5 to 7.5, the necessary current for tripping ranges from 6.67 .mu.A to 73.6 .mu.A. It can happen that the current drawn by the memory cells 12,14 is not sufficient to an enable such tripping currents to be obtained.
One could think of resolving the problem by resizing of the latch 16 or augmenting the number of memory cells 12,14. In the first case, making the pull-up resistor 32 more resistive, one would make the latch 16 too sensitive to noise, by excessively lowering its trip point. In the second case, more time would be needed for the erasing and programming the memory cells, not to mention the addition to the silicon space occupied by the protection circuit 10.
A technical problem addressed by the present invention is to create a CAM protection circuit with a latch that can successfully switch logic states even at high supply voltages.